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Coding and bit-error-rate-test blocks for a serial digital multi-gigabit communication system / David T. Carney.

by Carney, David T.

Digital communications

Error-correcting codes (Information theory)

Signal theory (Telecommunication)

165 leaves : ill. ; 29 cm.

Advisor: Dr. Edward Chandler.

Committee members: Dr. Steven Reyer, Dr. Teodoro Robles.

Introduction -- Literature review -- Error correction code functional block -- Bit-error-rate-test functional block -- Implementation and integration results -- Conclusions and future work -- References -- Bibliography -- Appendix A) ECC block datasheet; B) BERT block datasheet.

The project involves serial digital multi-gigabit communication systems that are emerging for use in chip-to-chip applications in digital systems. These systems communicate data using very high speed point-to-point serial links in a switch fabric architecture between processors and peripherals in digital systems. The major purpose of this project is to develop two reusable building blocks for use on projects containing serial digital multi-gigabit communication systems. The reusable building blocks are an error correcting code (ECC) encoder and decoder appropriate for these systems and a bit-error-rate-tester (BERT). Both of these building blocks are designed using digital logic in Very High Speed Integrated Circuit Hardware Description Language (VHDL) to be implemented in a field programmable gate array (FPGA) that contains multi-gigabit serial transceivers.

The project includes a detailed investigation of serial digital multi-gigabit communication systems that was required to determine an appropriate ECC design. Elements of the investigation include the communication channel and bandwidth, random and deterministic noise sources and effects, characteristics of the transmitted data, and a comparison of different types of ECCs. The ECC designed in this project consisted of a maximum run length code state inside of a w-error correcting primitive BCH code. The overall code word size is 63 bits. A detailed description of the logic design for this code is provided.

The project also includes some investigation into bit-error-rate test methodologies. Some information on the statistical nature of bit-error-rate measurements is developed as well as discussion of different types of data patterns. Three bit-error-rate test patterns are implemented in the BERT block and they are a programmable data word pattern, a 211 - 1 pseudorandom bit sequence (PRBS) pattern, and a 231 - 1 PRBS pattern. A detailed description of the logic design for the BERT block is provided. The design of the BERT block is efficient enough to support data rates up to the maximum of the Altera Stratix GX FPGA.

In the project, the ECC block is implemented in an Altera Stratix GX FPGA. The BERT block is used as the data source and also to measure the bit error rate. The bit error rate performance is compared for the coded data and the uncoded data running at approximately the information data rate of the coded data. Two physical channels are used in the comparison, one 10-inch backplane channel and one 40-inch backplane channel. The ECC block design of this project is not effective in the 40-inch inch backplane channel and results in a higher bit error rate than uncoded data. The ECC block is effective in the 10-inch backplane channel, but the bit error rate without coding is already much lower than the target rate. The test results indicate that the ECC block may be more effective when used with equalization. They also indicate that a code with similar error correcting capabilities but a higher code rate may also improve performance, but detailed investigation of this is left as future work.

https://msoe.tind.io/record/915

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